64-Digit BCD Multiplier

Programmed a BCD multiplier with 32-bit registers using VisUAL 2, (original ARM instruction set supported with the exception of the MUL instruction) which could multiply any two 64 digit Binary coded decimal numbers (signed or unsigned) with the aim to optimise clock cycles. 

Final script ran in just over 100,000 cycles; one of the fastest in the cohort and was better optimised than the lead professor’s solution. 
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A priority was put into making sure that the single digit multiplication and addition was as short as possible, with minor improvements in clock cycles here resulting in major improvements with in clock cycles for the whole program. This involved using a lookup table to calculate single digit multiplications, as well as a clever method of adding registers together (found through research online). Code is available for perusal on my Github.